In manufacturing steps of semiconductor elements of recent years, processing techniques for densification and miniaturization are becoming increasingly important. CMP (Chemical Mechanical Polishing) technique, as one of the processing techniques, has become an essential technique for forming Shallow Trench Isolation (hereinafter, referred to as “STI” in some cases), flattening pre-metal insulating materials or interlayer insulating materials, and forming plugs or embedded metal wires, in manufacturing steps of semiconductor elements.
Conventionally, in manufacturing steps of semiconductor elements, insulating materials such as silicon oxide, which are formed by a CVD (Chemical Vapor Deposition) method, a spin-coating method or the like, are flattened by CMP. In the CMP, silica-based polishing liquids comprising silica particles such as colloidal silica and fumed silica as abrasive grains are generally used. The silica-based polishing liquids are manufactured by performing grain growth of abrasive grains by methods such as thermal decomposition of silicon tetrachloride and adjusting pH. However, these silica-based polishing liquids have a technical problem of a low polishing rate.
Incidentally, STI is used for element isolation in integrated circuits in the generation after a design rule of 0.25 μm. In STI formation, CMP is used for removing an extra part of an insulating material deposited on a base substrate. In order to stop polishing in CMP, a stopper (polishing stop layer) having a slow polishing rate is formed under the insulating material. Silicon nitride, polysilicon or the like is used for a stopper material (constituent material of stopper), and the polishing selection ratio of the insulating material with respect to the stopper material (polishing rate ratio: polishing rate of insulating material/polishing rate of stopper material) is desirably high. Conventional silica-based polishing liquids have a low polishing selection ratio of the insulating material with respect to the stopper material, about 3, and tend not to have properties which can withstand practical use for STI.
Moreover, in recent years, as cerium oxide-based polishing liquids, polishing liquids for semiconductors, using high-purity cerium oxide particles, have been used (for example, refer to the following Patent Literature 1).
Incidentally, in recent years, achievement of further miniaturization of wires has been required in manufacturing steps of semiconductor elements, and polishing scratch generated during polishing have become a problem. Specifically, when polishing is performed using conventional cerium oxide-based polishing liquids, generation of fine polishing scratch gives no problem as long as the size of the polishing scratch is smaller than the conventional wire width, but becomes a problem in the case where further miniaturization of wires is tried to be achieved.
For this problem, in the above-described cerium oxide-based polishing liquids, the average particle diameter of cerium oxide particles is tried to be reduced. However, if the average particle diameter is reduced, the polishing rate may be decreased due to a decrease in the mechanical action. Even if both a polishing rate and polishing scratch are tried to be achieved by controlling the average particle diameter of cerium oxide particles in this manner, it is extremely difficult to achieve the exacting requirement of recent years for polishing scratch while maintaining a polishing rate.
In response to this, polishing liquids using particles of a hydroxide of a tetravalent metal element have been studied (for example, refer to the following Patent Literature 2). Moreover, manufacturing methods of particles of a hydroxide of a tetravalent metal element have also been studied (for example, refer to the following Patent Literature 3). These techniques aim at reducing polishing scratch due to particles, by minimizing the mechanical action as much as possible while maintaining the chemical action of the particles of a hydroxide of a tetravalent metal element.
Furthermore, other than reducing of polishing scratch, a base substrate having irregularities is required to be flatly polished. Using the above-described STI as an example, the polishing selection ratio of the insulating material that is a material to be polished (for example, silicon oxide) is required to be improved with respect to the polishing rate of the stopper material (for example, silicon nitride, polysilicon). In order to solve them, addition of various additives to polishing liquids has been studied. For example, a technique for improving the polishing selection ratio in a base substrate having wires with different wire densities in the same plane by adding additives to polishing liquids is known (for example, refer to the following Patent Literature 4). Moreover, addition of additives to cerium oxide-based polishing liquids for controlling the polishing rate and improving global flatness is known (for example, refer to the following Patent Literature 5).